Distributed Intracortical Neural Interfacing: Network protocol design

Distributed Intracortical Neural Interfacing: Network protocol design New high-performance neural interfacing approaches are demanded for today’s Brain-Machine Interfaces (BMIs). In this paper, we present the architecture of a wireless network of implantable microsystems (Brain-ASNET: Brain Area Sensor NETwork). As well, we introduce an energy-efficient ad-hoc network protocol for the desired network, along with a method to overcome issue of variable packet length caused by bit stuffing process in HDLC standard protocol. To implement the idea, architecture and design of a System-on-a-Chip (SoC) is also presented. The SoC can be configured to be used either as a sensor node chip or the network coordinator’s RF front-end and network controller. The SoC is designed and laid-out in an IBM 0.13μm CMOS process. The post-layout simulation results show energy efficiency of the designed ad-hoc network protocol and low power dissipation of the SoC. The whole chip, including all functional and peripheral integrated components, consumes 138μW and 412μW, at 1.2V, configured in a synchronized network as a sensor node and the coordinator, respectively.